1. Field of the Invention
The present invention relates to a system with memory modules for controlling data input and output, and more particularly, to a system having a multiplicity of memory modules for controlling data input and output from and to a common data line by connecting selected memory modules to the common data line.
2. Description of the Related Art
A semiconductor memory device such as a dynamic random access memory (DRAM) can be used as a main memory in a system such as a computer. A memory using semiconductor memory devices generally has memory modules, such as dual in-line memory modules (DIMM) and single in-line memory modules (SIMM). A memory may be required to include a plurality of memory modules for operations of a system. In such a system, each of the memory modules uses a common data line. For instance, assuming that a main memory has a capacity of 32M bytes and is made with DIMMs each of which has a capacity of 8M bytes and made of four 16M (1Mxc3x9716) DRAMs, the main memory of 32M bytes requires four slots, i.e., four DIMMs. Since the number of data bus lines is 64 and the number of data pins per DIMM is 64, the main memory of 32M bytes requires a multiplicity of data pins. Thus, four DIMMs constituting the main memory of 32M bytes use a common data bus line of a system. As the capacity of the main memory is increased, the necessity of using a common data line is increased.
The capacitance per data pin of a DIMM module is 20xcx9c25 pF. Thus, when the 32M byte memory is composed of four DlMMs of 1Mxc3x9764, the capacitance per data pin becomes approximately 80xcx9c100 pF. Thus, the capacitance per data pin is so great that an increase in the load of an output driver increases power consumption, and that speed for writing and reading data is remarkably reduced.
It is an object of the present invention to provide a memory module with minimized load capacitance per data pin to improve speed of writing and reading data and of the memory module.
To achieve the above and other objects, according to an aspect of the present invention, there is provided a memory module system for controlling data output to a data bus line, the system comprising a multiplicity of memory modules each of which includes a control signal generation circuit for generating a connection control signal having a width of activation corresponding to a burst length of output data, wherein the control signal generation circuit has a read control unit for activating input data during output of data of a predetermined burst length in a read mode to generate a read control signal, the read control unit receiving CAS latency information, a read command signal and burst length information of read data, and a multiplicity of switching units for electrically connecting output terminals of the memory modules to the data bus line in response to activation of the connection control signal. In the memory module system according to the present invention, the memory modules for receiving outputting data are electrically connected to the data bus line in response to activation of the connection control signals. The control signal generation circuit further comprises a write information generation unit. The write information generation unit receives a write command signal and burst length information of write data, and it is activated in a write mode during inputting data of a predetermined burst length to generate a write control signal.
In a memory module system for controlling data input and output according to the present invention, selected memory modules are connected to a data line during a data burst length in which data is input and output. Thus, load is minimized per data pin, so that speed of writing and reading data is improved.